The present invention relates to a scan operation executing system and, more particularly, to a main scan operation executing system for diagnosing a main processor which has a scan path.
In order to perform diagnosis for a main processor, a scan path diagnostic system in which flip-flop inputs and outputs in the main processor are switched to form a single path of the flip-flops and a diagnostic processor which samples information in the scan path have been conventionally used. In the conventional scan path diagnostic system, a diagnostic processor issues a scan operation execution request by using an exclusive diagnostic interface to a processor to shift information in the scan path, thereby sampling the information.
FIG. 2 is a timing chart for explaining an operation performed in the above scan path diagnostic system. This operation will be described below with reference to FIG. 2. In order to perform a diagnostic operation for a main processor, a diagnostic processor outputs a diagnostic activation signal (timing 1) to initialize a diagnostic control unit 9 in the main processor. Since an internal state of the diagnostic control unit 9 is not definite when a diagnostic command is issued, the diagnostic activation signal must be output to perform initialization prior to the command. At the same time, a scan mode set flip-flop (to be referred to as a scan mode F/F hereinafter) in the main processor is reset. When a scan operation execution request is issued by the diagnostic command (timing 3), the scan mode F/F is set by this request (timing 4). Thereafter, data in a scan path 7 is output at the same time as scan data is input in units of clocks to the scan path 7 (after timing 4), and this operation is continuously performed until all items of information in a flip-flop of interest in the main processor are completely sampled. The scan operation is classified into a scan-out operation for sampling information from the main processor and a scan-in operation for loading information in the main processor. In either operation, the task of loading data in the main processor must be performed after the data is sampled from the main processor. Therefore, the diagnostic processor issues the scan operation execution request twice. In addition, unexpected data is sequentially inserted in flip-flops during the scan operation. In order to prevent the illegal operation in an external interface or the internal logic, therefore, the main processor performs inhibition for an external interface signal or an internal operation by using a scan mode signal output from the scan mode F/F.
In the above conventional scan operation executing system, however, upon issuing of the two scan operation execution requests performed in a series of scan-in and scan-out operations, the scan mode F/F is reset by the diagnostic activation signal. Since a timing at which the scan mode signal is inactivated is generated upon issuance of the second scan operation execution request, therefore, an illegal operation may occur in the external interface or the internal logic.